The present invention is related in general to the field of semiconductor devices and more specifically to very thin wire-bonded semiconductor packages.
An ongoing trend in the semiconductor industry is the need for devices with a thinner profile. One of the major hurdles to achieve thinner devices is an inherent feature of the wire ball-bonding technology, which is the dominant assembly technique for the majority of integrated circuit chips. In the wire ball-bonding process, a free air ball, approximately spherical in shape, is created at the tip of the wire by using a flame or a spark technique. It is unavoidable that the heat necessary to melt a small volume of the wire for forming the ball also spreads along a certain distance of the wire, without actually melting the metal. The extent of the heat-affected zone depends, among other parameters, on the thermal conductivity of the wire metal. Most commonly, gold, copper, aluminum, or alloys of these metals are used as wire materials. When the ball cools and solidifies, the cooling of the heat-affected zone causes a re-crystallization of the wire; a result of which is that the originally microcrystalline metal tends to develop fewer and larger crystals. These crystals, in turn, are easier to separate under force and thus reduce the mechanical strength of the wire in the heat-affected zone.
In the conventional ball-bonding technology, the reduction of mechanical strength in the heat-affected zone is compensated by a procedure in which the ball is first attached to the contact pad (for example, of the integrated circuit), and the wire is then allowed to attain a vertical position over the ball for the length of the heat-affected zone. Only after this vertical stretch is the wire formed into the curvature and bending of the loop which bridges the distance to the contact pad of the stitch bond. The usually high loop necessitated by the heat-affected zone is a hallmark of wire ball bonding. Would the curvature and bending of the wire initiate directly over the ball, the wire would easily shear off and break.
A need has therefore arisen for a coherent, low-cost method of wire ball bonding without the need of high, arching wire loops. The innovative wire bonding method should use the installed equipment base so that no investment in new manufacturing machines is needed. The method should be flexible enough to be applied for different semiconductor product families and a wide spectrum of design and assembly variations, and should achieve improvements toward the goals of improved process yields and device reliability.
One embodiment of the invention is an assembly of a semiconductor chip having an integrated circuit (IC) including at least one contact pad on its surface, wherein the contact pad has a metallization suitable for wire bonding, and an interconnect bonded to said contact pad. This interconnect includes a wire attached to the pad by ball bonding, a loop in the wire closed by bonding the wire to itself near the ball, and a portion of the remainder of the wire extended approximately parallel to the surface of the chip. The interconnect can be confined to a space equal to or less than about three ball heights from the surface.
In another embodiment of the invention, an electrically insulating substrate with first and second surfaces and a plurality of electrically conductive routing strips integral with the substrate, has a first plurality of contact pads disposed on the first surface and a second plurality of contact pads disposed on the second surface. An IC chip with a plurality of bonding pads is attached to the first substrate surface. At least some of the bonding pads have a wire interconnect attached by ball bonding. The interconnect has a loop in the wire which is closed by bonding the wire to itself near the ball, and a portion of the remainder of the wire extends approximately parallel to the surface, spanning the chip surface to the edge of the chip. Each interconnect can thus be confined to a space equal to or less than about three ball heights from the active surface. Finally, each wire is bonded to its respective substrate contact pad on the first substrate surface, and chip and wires are encapsulated. Interconnection elements may be attached to each of the contact pads on the second substrate surface.
Another embodiment of the invention is a method for forming a low profile wire bond for a low profile package for a semiconductor chip having on its surface an IC and at least one contact pad with a metallization suitable for wire bonding. In this method, a wire is attached to the pad by ball bonding. A loop is then formed in the wire and the loop is closed by stitching the wire to itself near said ball. As a result, the mechanical strength of the recrystallized portion of the wire near the ball is improved. The loop may be formed at a distance less than about three ball heights from the chip surface.
Embodiments of the present invention are related to thin devices and packages, which are, for example, required in stacks of memory devices and miniaturized products. The ICs for these and similar products can be found in many semiconductor device families such as standard linear and logic products, digital signal processors, microprocessors, wireless devices, and digital and analog devices. The embodiments apply to wires of various metals, such as gold, copper, or aluminum.
It is a technical advantage of one or more embodiments of the invention that the embodiments can reach the goals of the invention with a low-cost manufacturing method without the cost of equipment changes and new capital investment, by using the installed fabrication equipment base, especially established automated wire bonding machines.
Another advantage which may flow from one or more embodiments of the invention is to produce thin outline devices with packages having interconnection elements including reflowable material, or just with pressure contacts. Other embodiments of thin outline devices include packages with leadframes. Embodiments of the invention generally apply to semiconductor package types such as PDIPs, SOICs, QFPs, SSOPs, TQFPs, TSSOPs, TVSOPs, and Ball Grid Array devices employing leadframes.
The technical advances represented by certain embodiments of the invention will become apparent from the following description of the preferred embodiments of the invention, when considered in conjunction with the accompanying drawings and the novel features set forth in the appended claims.